Makefiles

A basic build rule set — targets, their dependencies, and the recipe to build them, so make only redoes the work that actually needs redoing.

CC = gcc
CFLAGS = -Wall -g

program: main.o point.o
	gcc -o program main.o point.o

main.o: main.c point.h
	$(CC) $(CFLAGS) -c main.c

point.o: point.c point.h
	$(CC) $(CFLAGS) -c point.c

clean:
	rm -f program *.o

Each rule is target: dependencies, followed by a recipe line that has to start with an actual tab character, not spaces — the one syntax detail that trips up basically everyone the first time. make compares file timestamps and only rebuilds a target if one of its dependencies is newer, which is the entire point over just recompiling everything from scratch every time.